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features ? single 2.3v - 3.6v or 2.7v - 3.6v supply ? serial peripheral interface (spi) compatible ? supports spi modes 0 and 3 ? 66 mhz maximum operating frequency ? clock-to-output (t v ) of 6 ns maximum ? flexible, optimized erase architecture for code + data storage applications ? uniform 4-kbyte block erase ? uniform 32-kbyte block erase ? uniform 64-kbyte block erase ? full chip erase ? individual sector protection with global protect/unprotect feature ? four sectors of 64 kbytes each ? hardware controlled locking of protected sectors via wp pin ? 128-byte programmable otp security register ? flexible programming ? byte/page program (1 to 256 bytes) ? fast program and erase times ? 1.0 ms typical page program (256 bytes) time ? 50 ms typical 4-kbyte block erase time ? 250 ms typical 32-kbyte block erase time ? 450 ms typical 64-kbyte block erase time ? automatic checking and reporting of erase/program failures ? jedec standard manufacturer and device id read methodology ? low power dissipation ? 7 ma active read current (typical at 20 mhz) ? 15 a deep power-down current (typical) ? endurance: 100,000 program/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150-mil wide) ? 8-pad ultra thin dfn (5 x 6 x 0.6 mm) 1. description the at25df021 is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based appl ications in which program code is shad- owed from flash memory into embedded or external ram for execution. the flexible erase architecture of the at25df021, with its erase granularity as small as 4 kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. 2-megabit 2.3-volt or 2.7-volt minimum spi serial flash memory at25df021 (not recommended for new designs) 3677f?dflash?5/2013
2 3677f?dflash?5/2013 at25df021 the physical sectoring and the erase block sizes of the at25df021 have been optimized to meet the needs of today's code and data storage applications. by optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must re side by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. this increased memory space efficiency allows additional code routines and data storage segmen ts to be added while still maintaining the same overall device density. the at25df021 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. by providing the ability to individually pro- tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applica- tions where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. in addition to individual sector protection capabili- ties, the at25df021 incorporates global protect and global unprotect features that allow the entire memory array to be either protected or unprotected all at once. this reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. the device also contains a specialized otp (one-time programmable) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. specifically designed for use in 2.5-volt or 3-volt systems, th e at25df021 supports read, pro- gram, and erase operations with a supply voltage range of 2.3v to 3.6v or 2.7v to 3.6v. no separate voltage is required for programming and erasing.
3 3677f?dflash?5/2013 at25df021 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched in on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. - input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched in on the rising edge of sck. data present on the si pin will be ignored whenever the device is deselected ( cs is deasserted). - input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. the so pin will be in a high-impedance state whenever the device is deselected ( cs is deasserted). - output wp write protect: the wp pin controls the hardware locking feature of the device. please refer to ?protection commands and features? on page 12 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. please refer to ?hold? on page 29 for additional details on the hold operation. the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. - power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. - power
4 3677f?dflash?5/2013 at25df021 3. block diagram figure 3-1. block diagram 4. memory array to provide the greatest flexibility, the memory array of the at25df021 can be erased in four lev- els of granularity including a full chip erase. in addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. the size of the physical sectors is optimized fo r both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. the memory architecture diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. figure 2-1. 8-soic top view figure 2-2. 8-udfn (top view) 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si cs so wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si flash memory array y-gating cs sck so si y-decoder address latch x-decoder i/o buffers and latches control and protection logic sram data buffer wp interface control and logic hold
5 3677f?dflash?5/2013 at25df021 figure 4-1. memory architecture diagram internal sectoring for 64kb 32kb 4kb 1-256 byte sector protection block erase block erase block erase page program function (d8h command) (52h command) (20h command) (02h command) 4kb 03ffffh ? 03f000h 256 bytes 03ffffh ? 03ff00h 4kb 03efffh ? 03e000h 256 bytes 03feffh ? 03fe00h 4kb 03dfffh ? 03d000h 256 bytes 03fdffh ? 03fd00h 4kb 03cfffh ? 03c000h 256 bytes 03fcffh ? 03fc00h 4kb 03bfffh ? 03b000h 256 bytes 03fbffh ? 03fb00h 4kb 03afffh ? 03a000h 256 bytes 03faffh ? 03fa00h 4kb 039fffh ? 039000h 256 bytes 03f9ffh ? 03f900h 4kb 038fffh ? 038000h 256 bytes 03f8ffh ? 03f800h 4kb 037fffh ? 037000h 256 bytes 03f7ffh ? 03f700h 4kb 036fffh ? 036000h 256 bytes 03f6ffh ? 03f600h 4kb 035fffh ? 035000h 256 bytes 03f5ffh ? 03f500h 4kb 034fffh ? 034000h 256 bytes 03f4ffh ? 03f400h 4kb 033fffh ? 033000h 256 bytes 03f3ffh ? 03f300h 4kb 032fffh ? 032000h 256 bytes 03f2ffh ? 03f200h 4kb 031fffh ? 031000h 256 bytes 03f1ffh ? 03f100h 4kb 030fffh ? 030000h 256 bytes 03f0ffh ? 03f000h 4kb 02ffffh ? 02f000h 256 bytes 03efffh ? 03ef00h 4kb 02efffh ? 02e000h 256 bytes 03eeffh ? 03ee00h 4kb 02dfffh ? 02d000h 256 bytes 03edffh ? 03ed00h 4kb 02cfffh ? 02c000h 256 bytes 03ecffh ? 03ec00h 4kb 02bfffh ? 02b000h 256 bytes 03ebffh ? 03eb00h 4kb 02afffh ? 02a000h 256 bytes 03eaffh ? 03ea00h 4kb 029fffh ? 029000h 256 bytes 03e9ffh ? 03e900h 4kb 028fffh ? 028000h 256 bytes 03e8ffh ? 03e800h 4kb 027fffh ? 027000h 4kb 026fffh ? 026000h 4kb 025fffh ? 025000h 4kb 024fffh ? 024000h 256 bytes 0017ffh ? 001700h 4kb 023fffh ? 023000h 256 bytes 0016ffh ? 001600h 4kb 022fffh ? 022000h 256 bytes 0015ffh ? 001500h 4kb 021fffh ? 021000h 256 bytes 0014ffh ? 001400h 4kb 020fffh ? 020000h 256 bytes 0013ffh ? 001300h 256 bytes 0012ffh ? 001200h 256 bytes 0011ffh ? 001100h 256 bytes 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 bytes 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 bytes 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 bytes 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 bytes 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 bytes 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 bytes 000affh ? 000a00h 4kb 009fffh ? 009000h 256 bytes 0009ffh ? 000900h 4kb 008fffh ? 008000h 256 bytes 0008ffh ? 000800h 4kb 007fffh ? 007000h 256 bytes 0007ffh ? 000700h 4kb 006fffh ? 006000h 256 bytes 0006ffh ? 000600h 4kb 005fffh ? 005000h 256 bytes 0005ffh ? 000500h 4kb 004fffh ? 004000h 256 bytes 0004ffh ? 000400h 4kb 003fffh ? 003000h 256 bytes 0003ffh ? 000300h 4kb 002fffh ? 002000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 bytes 0001ffh ? 000100h 4kb 000fffh ? 000000h 256 bytes 0000ffh ? 000000h 64kb (sector 2) 64kb 64kb (sector 3) ? ? ? range ? ? ? 64kb 32kb 32kb ? ? ? block erase detail 32kb 32kb pa g e pro g ram detail page address block address range ? ? ? 64kb (sector 0) 32kb 32kb ? ? ? 64kb
6 3677f?dflash?5/2013 at25df021 5. device operation the at25df021 is controlled by a set of instruct ions that are sent from a host controller, com- monly referred to as the spi master. the spi master communicates with the at25df021 via the spi bus which is comprised of four signal lines: chip select ( c s), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at25df021 supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 6. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. all opcode, address, and data bytes are trans- ferred with the most-significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the at25df021 will be ignored by the device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation ( cs pin being deasserted and then reasserted). in addition, if the cs pin is deas- serted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the at25df021 memory array is 03ffffh, address bits a23-a18 are always ignored by the device. sck cs si so msb lsb msb lsb
7 3677f?dflash?5/2013 at25df021 table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 up to 66 mhz 3 1 1+ 03h 0000 0011 up to 33 mhz 3 0 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 up to 66 mhz 3 0 0 block erase (32 kbytes) 52h 0101 0010 up to 66 mhz 3 0 0 block erase (64 kbytes) d8h 1101 1000 up to 66 mhz 3 0 0 chip erase 60h 0110 0000 up to 66 mhz 0 0 0 c7h 1100 0111 up to 66 mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 66 mhz 3 0 1+ protection commands write enable 06h 0000 0110 up to 66 mhz 0 0 0 write disable 04h 0000 0100 up to 66 mhz 0 0 0 protect sector 36h 0011 0110 up to 66 mhz 3 0 0 unprotect sector 39h 0011 1001 up to 66 mhz 3 0 0 global protect/unprotect use write status register command read sector protection registers 3ch 0011 1100 up to 66 mhz 3 0 1+ security commands program otp security register 9bh 1001 1011 up to 66 mhz 3 0 1+ read otp security register 77h 0111 0111 up to 66 mhz 3 2 1+ status register commands read status register 05h 0000 0101 up to 66 mhz 0 0 1+ write status register 01h 0000 0001 up to 66 mhz 0 0 1 miscellaneous commands read manufacturer and device id 9fh 1001 1111 up to 66 mhz 0 0 1 to 4 deep power-down b9h 1011 1001 up to 66 mhz 0 0 0 resume from deep power-down abh 1010 1011 up to 66 mhz 0 0 0
8 3677f?dflash?5/2013 at25df021 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been speci- fied. the device incorporates an internal address counter that automatically increments on every clock cycle. two opcodes (0bh and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to read data from the device. the 0bh opcode can be used at any clock frequency up to the maximum specified by f clk , and the 03h opcode can be used for lower fr equency read operations up to the maximum specified by f rdlf . to perform the read array operation, the c s pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0bh opcode is used for the read array operation. after the three address bytes (and the dummy byte if using opcode 0bh) have been clocked in, additional clock cycles will result in data being out put on the so pin. the data is always output with the msb of a byte first. when the last byte (03ffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the c s pin will terminate the read operation and put the so pin into a high-imped- ance state. the c s pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array - 0bh opcode figure 7-2. read array - 03h opcode sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance
9 3677f?dflash?5/2013 at25df021 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 12 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and pro- gram it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be pro- grammed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 13 ), then the byte/page program command will not be executed, and the device will return to the idle state once the c s pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programmin g error arises, it will be indicated by the epe bit in the status register.
10 3677f?dflash?5/2013 at25df021 figure 8-1. byte program figure 8-2. page program 8.2 block erase a block of 4, 32, or 64 kbytes can be erased (all bits set to the logical ?1? state) in a single oper- ation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status reg- ister to a logical ?1? state. to perform a block erase, the c s pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the device will erase the appropriate block. the erasing of the block is internally self- timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14-a0 will be ignored, and for a 64-kbyte erase, address bits a15-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the c s pin is deas- serted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
11 3677f?dflash?5/2013 at25df021 if the address specified by a23-a0 points to a memory location within a sector that is in the pro- tected state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the c s pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an er ase error occurs, it will be indicat ed by the epe bit in the status register. figure 8-3. block erase 8.3 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been pre- viously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the chip erase command. there is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if any sector of the memory array is in the protected state, then the chip erase command will not be executed, and the device will return to the idle state once the c s pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the cs pin is deasserted on uneven byte boundaries or if a sector is in the protected state. sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
12 3677f?dflash?5/2013 at25df021 while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an er ase error occurs, it will be indicat ed by the epe bit in the status register. figure 8-4. chip erase 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status regis- ter to a logical ?1? state. the wel bit must be set before a by te/page program, erase, protect sector, unprotect sector, program otp security register, or write status register command can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the com- mand will not be executed. to issue the write enable command, the c s pin must first be assert ed and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-1. write enable sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance
13 3677f?dflash?5/2013 at25df021 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status reg- ister to the logical ?0? state. with the wel bit reset, all byte/page program, erase, protect sector, unprotect sector, program otp security register, and write status register com- mands will not be executed. other conditions can also cause the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the c s pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable 9.3 protect sector every physical 64-kbyte sector of the device has a corresponding single-bit sector protection register that is used to control the software protection of a sector. upon device power-up, each sector protection register will default to the logi cal ?1? state indicating t hat all sectors are pro- tected and cannot be programmed or erased. issuing the protect sector command to a particular sector address will set the corresponding sector protection register to the logical ?1? state. the following table outlines the two states of the sector protection registers. before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the protect sector command, the cs pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be pro- tected. any additional data clocked into the device will be ignored. when the c s pin is deasserted, the sector protection register corresponding to the physical sector addressed by a23-a0 will be set to the logical ?1? state, and the sector itself will then be protected from sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance table 9-1. sector protection register values value sector protection status 0 sector is unprotected and can be programmed and erased. 1 sector is protected and cannot be programmed or erased. this is the default state.
14 3677f?dflash?5/2013 at25df021 program and erase operations. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the c s pin is deas- serted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation. when the device aborts the protect sector opera- tion, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous protecting or unprotecting of sectors, the sector protection registers can themselves be locked from updates by using the sprl (sector protec- tion registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the protect sector command will be ignored, and the device will reset the wel bit in the status reg- ister back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-3. protect sector 9.4 unprotect sector issuing the unprotect sector command to a particular sector address will reset the correspond- ing sector protection register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector pro- tection register that is used to control the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the unprotect sector command, the c s pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designat- ing any address within the sector to be unprotected must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the c s pin is deasserted, the sector protection register corresponding to the sector addressed by a23-a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the sta- tus register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the c s pin is deas- serted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector pro- tection registers can themselves be locked from updates by using the sprl (sector protection sck cs si so msb msb 23 1 0 00110110 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
15 3677f?dflash?5/2013 at25df021 registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the unprotect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-4. unprotect sector 9.5 global protect/unprotect the global protect and global unprotect features can work in conjunction with the protect sec- tor and unprotect sector functions. for example, a system can globally protect the entire memory array and then use the unprotect sector command to individually unprotect certain sec- tors and individually reprotect them later by using the protect sector command. likewise, a system can globally unprotect the entire memory array and then individually protect certain sec- tors as needed. performing a global protect or global unprotect is accomplished by writing a certain combina- tion of data to the status register using the write status register byte 1 command (see ?write status register? on page 25 for command execution details). the write status register com- mand is also used to modify the sprl (sector protection registers locked) bit to control hardware and software locking. to perform a global protect, the appropriate wp pin and sprl conditions must be met, and the system must write a logical ?1? to bits 5, 4, 3, and 2 of the first byte of the status register. con- versely, to perform a global unprotect, the same wp and sprl conditions must be met but the system must write a logical ?0? to bits 5, 4, 3, and 2 of the first byte of the status register. table 9-2 details the conditions necessary for a global protect or global unprotect to be performed. sck cs si so msb msb 23 1 0 00111001 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
16 3677f?dflash?5/2013 at25df021 essentially, if the sprl bit of the status register is in the logical ?0? state (sector protection registers are not locked), then writing a 00h to the first byte of the status register will perform a global unprotect without changing the state of the sprl bit. similarly, writing a 7fh to the first byte of the status register will perform a global protect and keep the sprl bit in the logical ?0? state. the sprl bit can, of course, be changed to a logical ?1? by writing an ffh if software-lock- ing or hardware-locking is desired along with the global protect. if the desire is to only change the sprl bit without performing a global protect or global unpro- tect, then the system can simply write a 0fh to the first byte of the status register to change the table 9-2. valid sprl and global protect/unprotect conditions wp state current sprl value new write status register byte 1 data protection operation new sprl value bit 7 6 5 4 3 2 1 0 00 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 0 1 x x x x x x x x no change to the current protection level. all sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. the sector protection registers are hard-locked and cannot be changed when the wp pin is low and the current state of sprl is 1. therefore, a global protect/unprotect will not occur. in addition, the sprl bit cannot be changed (the wp pin must be high in order to change sprl back to a 0). 10 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 11 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x no change to the current protection level. all sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. the sector protection registers are soft-locked and cannot be changed when the current state of sprl is 1. therefore, a global protect/unprotect will not occur. however, the sprl bit can be changed back to a 0 from a 1 since the wp pin is high. to perform a global protect/unprotect, the write status register command must be issued again after the sprl bit has been changed from a 1 to a 0. 0 0 0 0 0 1 1 1 1 1
17 3677f?dflash?5/2013 at25df021 sprl bit from a logical ?1? to a logical ?0? provided the wp pin is deasserted. likewise, the sys- tem can write an f0h to change the sprl bit from a logical ?0? to a logical ?1? without affecting the current sector protection status (no changes will be made to the sector protection registers). when writing to the first byte of the status register, bits 5, 4, 3, and 2 will not actually be modi- fied but will be decoded by the device for the purposes of the global protect and global unprotect functions. only bit 7, the sprl bit, will actually be modified. therefore, when reading the first byte of the status register, bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of the wp pin and the sector protection status. please refer to ?read status register? on page 22 and table 11-1 on page 22 for details on the status register format and what values can be read for bits 5, 4, 3, and 2. 9.6 read sector protection registers the sector protection registers can be read to determine the current software protection status of each sector. reading the sector protection registers, however, will not determine the status of the wp pin. to read the sector protection register for a particular sector, the c s pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. after the last address byte has been clocked in, the device will begin outputting data on the so pin during every subse- quent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. deasserting the c s pin will terminate the read operation and put the so pin into a high-imped- ance state. the c s pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector protection registers, the software protection status (swp) bits in the status register ca n be read to determine if all, some, or none of the sectors are software protected (refer to ?read status register? on page 22 for more details). figure 9-5. read sector protection register table 9-3. read sector protection register - output data output data sector protection register value 00h sector protection register value is 0 (sector is unprotected). ffh sector protection register value is 1 (sector is protected). sck cs si so msb msb 23 1 0 00111100 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte high-impedance
18 3677f?dflash?5/2013 at25df021 9.7 protected states and the write protect ( wp) pin the wp pin is not linked to the memory array itself and has no direct effect on the protection sta- tus or lockdown status of the memory array. instead, the w p pin, in conjunction with the sprl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met- the wp pin must be asserted and the sprl bit must be in the logical ?1? state. when hardware locking is active, the sector pro tection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the protect sector, unprotect sector, and write status register commands will be ignored. in order to modify the protection status of a sector, the w p pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state using the write status register command. when resetting the sprl bit back to a logical ?0?, it is not possible to perform a global protect or global unprotect at the same time since the sector protection registers remain soft-locked until after the write status register command has been executed. if the w p pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to v cc , the sprl bit in the status register can still be set to a logical ?1? to lock the sector protection registers. this provides a software locking ability to prevent erroneous protect sector or unprotect sector com- mands from being processed. when changing the sprl bit to a logical ?1? from a logical ?0?, it is also possible to perform a global protect or global unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the first byte of the status register. tables 9-4 and 9-5 detail the various protection and locking states of the device. note: 1. ?n? represents a sector number table 9-4. sector protection register states wp sector protection register n (1) sector n (1) x (don't care) 0 unprotected 1 protected
19 3677f?dflash?5/2013 at25df021 10. security commands 10.1 program otp security register the device contains a specialized otp (one-time programmable) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. the otp security register is independent of the main flash memory array and is comprised of a total of 128 bytes of memory divided into two por- tions. the first 64 bytes (byte locations 0 through 63) of the otp security register are allocated as a one-time user-programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64 bytes of the otp security register (byte locations 64 through 127) are factory programmed by adesto ? and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. the user-programmable portion of the otp security register does not need to be erased before it is programmed. in addition, the program otp security register command operates on the entire 64-byte user-programmable portion of the otp security register at one time. once the user-programmable space has been programmed with any number of bytes, the user-program- mable space cannot be programmed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. before the program otp security register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to program the otp security register, the c s pin must first be asserted and an opcode of 9bh must be clocked into the device followed by the three address bytes denoting the first byte table 9-5. hardware and software locking wp sprl locking sprl change allowed sector protection registers 0 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 01 hardware locked locked locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed. 1 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 11 software locked can be modified from 1 to 0 locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed. table 10-1. otp security register security register byte number 0 1 . . . 62 63 64 65 . . . 126 127 one-time user programmable factory programmed by adesto
20 3677f?dflash?5/2013 at25df021 location of the otp security regis ter to begin programming at. si nce the size of the user-pro- grammable portion of the otp security register is 64 bytes, the upper order address bits do not need to be decoded by the device. therefore, address bits a23-a6 will be ignored by the device and their values can be either a logical ?1? or ?0?. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. if the starting memory address denoted by a23-a0 does not start at the beginning of the otp security register memory space (a5-a0 are not all 0), then special circumstances regarding which otp security register locati ons to be programmed will appl y. in this situation, any data that is sent to the device that goes beyond the end of the 64-byte user-programmable space will wrap around back to the beginning of the otp security register. for example, if the starting address denoted by a23-a0 is 00003eh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at otp security register addresses 00003eh and 00003fh while the last byte of data will be programmed at address 000000h. the remaining bytes in the otp security register (addresses 000001h through 00003dh) will not be pro- grammed and will remain in the erased state (ffh). in addition, if more than 64 bytes of data are sent to the device, then only the last 64 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and pro- gram it into the appropriate otp security register locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 64 bytes of data were sent to the device, then the remaining bytes within the otp security register will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t otpp . the three address bytes and at least one complete byte of data must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programma- ble portion of the otp security register will not be programmed. the wel bit in the status register will be reset back to the logical ?0? state if the otp security register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the user-programmable portion of the otp security register was previously programmed. while the device is programming the otp security register, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t otpp time to determine if the data bytes have finished programming. at some point before the otp security register programming completes, the wel bit in the status register will be reset back to the logical ?0? state. if the device is powered-down during the otp security register program cycle, then the con- tents of the 64-byte user programmable portion of the otp security register cannot be guaranteed and cannot be programmed again. the program otp security register command utilizes the internal 256-buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued.
21 3677f?dflash?5/2013 at25df021 figure 10-1. program otp security register 10.2 read otp security register the otp security register can be sequentially read in a similar fashion to the read array oper- ation up to the maximum clock frequency specified by f clk . to read the otp security register, the c s pin must first be asserted and the opcode of 77h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the start- ing address location of the first byte to read within the otp security register. following the three address bytes, two dummy bytes must be clocked into the device before data can be output. after the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in otp security register data being output on the so pin. when the last byte (00007fh) of the otp security register has been read, the device will continue reading back at the beginning of the register (000000h). no delays will be incurred when wrapping around from the end of the register to the beginning of the register. deasserting the c s pin will terminate the read operation and put the so pin into a high-imped- ance state. the c s pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-2. read otp security register sck cs si so msb msb 23 1 0 10011011 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3336 35 34 31 32 29 30 opcode aaaa aaa a axx x msb msb ddddddd d d d address bits a23-a0 msb xxxxx x don't care data byte 1 high-impedance
22 3677f?dflash?5/2013 at25df021 11. status register commands 11.1 read status register the status register can be read to determine the device?s ready/busy status, as well as the sta- tus of many other functions such as hardware locking and software protection. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the c s pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of the status register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the sta- tus register is constantly being updated, so each repeating sequence will output new data. deasserting the c s pin will terminate the read status register operation and put the so pin into a high-impedance state. the c s pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. only bit 7 of the status register will be modified when using the write status register command. 2. r/w = readable and writable r = readable only table 11-1. status register format bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 sector protection registers are unlocked (default). 1 sector protection registers are locked. 6 res reserved for future use r 0 reserved for future use. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 wpp write protect ( wp) pin status r 0 wp is asserted. 1 wp is deasserted. 3:2 swp software protection status r 00 all sectors are software unprotected (all sector protection registers are 0). 01 some sectors are software protected. read individual sector protection registers to determine which sectors are protected. 10 reserved for future use. 11 all sectors are software protected (all sector protection registers are 1 ? default). 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy/bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation.
23 3677f?dflash?5/2013 at25df021 11.1.1 sprl bit the sprl bit is used to control whether the sector protection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and can- not be modified with the protect sector and unprotect sector commands (the device will ignore these commands). in addition, the global protect and global unprotect features cannot be per- formed. any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. when the sprl bit is in the logical ?0? state, all sector protection registers are unlocked and can be modified (the protect sector and unprotect sector commands, as well as the global pro- tect and global unprotect features, will be pr ocessed as normal). the sprl bit defaults to the logical ?0? state after device power-up. the reset command has no effect on the sprl bit. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sector protection regis- ters are unlocked) to a logical ?1? (sector protection registers are locked). in order to reset the sprl bit back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the sprl bit is the only bit of the status register that can be user modified via the write status register command. 11.1.2 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or pro- gram operation aborts for any reason such as an attempt to erase or program a protected region, or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 11.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 11.1.4 swp bits the swp bits provide feedback on the software protection status for the device. there are three possible combinations of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector command or the global protect feature. if the swp bits indicate that some of the sectors have been protected, then the individual sector pro- tection registers can be read with the read sector protection registers command to determine which sectors are in fact protected.
24 3677f?dflash?5/2013 at25df021 11.1.5 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page program, erase, protect sector, unprotect sector, program otp security register, or write status register commands. the wel bit defaults to the logical ?0 ? state after a device power-up or reset operation. in addition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? protect sector operation completes successfully or aborts ? unprotect sector operation completes successfully or aborts ? program otp security register operation completes successfully or aborts ? byte/page program operation completes successfully or aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1 ? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a byte/page program, erase, protect sector, unprotect sector, program otp secu- rity register, or write status register command must have been clocked into the device. 11.1.6 rdy/bsy bit the rdy/bsy bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. to poll the rdy/bsy bit to detect the completion of a program or erase cycle, new status register data must be continua lly clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 11-1. read status register sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 28 29 27 26 25 30 opcode msb msb dddddd dd d d msb dddddd d d d dd d d d st data atus register st data atus register st data atus register high-impedance
25 3677f?dflash?5/2013 at25df021 11.2 write status register the write status register command is used to modify the sprl bit of the status register and/or to perform a global protect or global unprotect operation. before the write status regis- ter command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. the one byte of data con- sists of the sprl bit value, a don?t care bit, four data bits to denote whether a global protect or unprotect should be performed, and two additional don?t care bits (see table 11-2 ). any addi- tional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status register will be modified , and the wel bit in the status register will be reset back to a logical ?0?. the values of bits 5, 4, 3, and 2 and the state of the sprl bit before the write status register command was executed (the prior state of the sprl bit) will determine whether or not a global protect or global unprotect will be performed. please refer to ?global protect/unprotect? on page 15 for more details. the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the sprl bit will not change, no potential global protect or unprotect will be performed, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register byte command will be ignored, and the wel bit in the status register will be reset back to the logical ?0? state. in order to reset the sprl bit to a logical ?0?, the wp pin must be deasserted. figure 11-2. write status register table 11-2. write status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sprl x global protect/unprotect x x sck cs si so msb 23 1 0 0000000 67 5 4 opcode 10 11 9 81415 13 12 1 msb dxddddx x status register in high-impedance
26 3677f?dflash?5/2013 at25df021 12. other commands and functions 12.1 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. since not all flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. once the identification process is complete, the application can then increase the clock fre- quency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the c s pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin out- putting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device information string length, which will be 00h indicating that no extended device information follows. after the extended device information string length byte is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the c s pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 43h 3 device id (part 2) 00h 4 extended device information string length 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 00011111 device id (part 1) family code density code 43h family code: 010 (at25df/26dfxxx series) density code: 00011 (2-mbit) 01000011 device id (part 2) sub code product version code 00h sub code: 000 (standard series) product version: 00000 (initial version) 00000000
27 3677f?dflash?5/2013 at25df021 figure 12-1. read manufacturer and device id 12.2 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the c s pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consump- tion state called the deep power-down mode. when the device is in the deep power-down mode, all commands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the c s pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the c s pin is deasserted. in addition, the device will default to the standby mode after a power-cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. sck cs si so 6 0 9fh 8 7 38 opcode 1fh 43h 00h 00h manufacturer id device id byte 1 device i d byte 2 extended device information string length high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
28 3677f?dflash?5/2013 at25df021 figure 12-2. deep power-down 12.3 resume from deep power-down in order to exit the deep power-down mode and resume normal device operation, the resume from deep power-down command must be issued. the resume from deep power-down com- mand is the only command that the device will recognized while in the deep power-down mode. to resume from the deep power-down mode, the c s pin must first be asserted and opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the c s pin is deasserted, the device will exit the deep power- down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the c s pin is deasserted, or if the c s pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 12-3. resume from deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
29 3677f?dflash?5/2013 at25df021 12.4 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in prog- ress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the c s pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the h o l d pin and c s pin are asserted. while in the hold mode, the so pin will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the h o l d pin must be deasserted during the sck low pulse. if the h o l d pin is deasserted during the sck high pulse, then the hold mode won?t end until the beginning of the next sck low pulse. if the c s pin is deasserted while the h o l d pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the wel bit in the status register back to the logical ?0? state. figure 12-4. hold mode sck cs hold hold hold hold
30 3677f?dflash?5/2013 at25df021 13. system considerations in an effort to continue our goal of maintaining world-class quality leadership, adesto has been performing extensive testing on the at25df021 that would not normally be done with a serial flash device. the testing that has been performed on the at25df021 involved extensive, non- stop reading of the memory array on pre-conditioned devices. the pre-conditioning of the devices, which entailed erasing and programming the entire memory array 10,000 times, was done to simulate a customer environment and to exercise the memory cells to a certain degree. the non-stop reading of the devices was done in three levels of granularity, with the first level involving a continuous, looped read of 256 bytes (a single page) of memory, the second level involving a continuous, looped-read of a 4-kbyte (16 pages) portion of memory, and the third level entailing non-stop reading of the entire memory array. read operations were performed at both +25c and +125c and with a supply voltage of 3.7v, which exceeds the specified data- sheet operating voltage range. the results of all of the extensiv e tests indicate that the contents of a portion of memory being read continuously could be altered after 800,000,000 read operations only if that portion of the memory was not erased or reprogrammed at all during the 800,000,000 read operations. if that portion of memory was reprogrammed at some point, then it would take another 800,000,000 read operations after reprogramming before the contents could potentially be altered. for exam- ple, if the serial flash is being used for boot code storage, then it would take 800,000,000 boot operations before that boot code may become altered, provided that the boot code was not updated or reprogrammed. if an application was to read the entire memory array non-stop at a clock frequency of 10mhz, it would take over 5 years to reach 800,000,000 read operations. adesto firmly believes that this extended testing result should not be a cause for concern. we also believe that most, if not all, applications will never read the same portion of memory 800,000,000 times throughout the life of the application without ever updating that portion of memory.
31 3677f?dflash?5/2013 at25df021 14. electrical specifications 14.1 absolute maximum ratings* temperature under bias ................................ -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature..................................... -65 ? c to +150 ? c all input voltages (including nc pins) with respect to ground .....................................-0.6v to +4.1v all output voltages with respect to ground .............................-0.6v to v cc + 0.5v 14.2 dc and ac operating range at25df021 (2.3v version) at25df021 (2.7v version) operating temperature (case) ind. -40 ? c to 85 ? c -40 ? c to 85 ? c v cc power supply 2.3v to 3.6v 2.7v to 3.6v 14.3 dc characteristics symbol parameter condition min typ max units i sb standby current cs, wp, hold = v cc , all inputs at cmos levels 25 50 a i dpd deep power-down current cs, wp, hold = v cc , all inputs at cmos levels 15 25 a i cc1 active current, read operation f = 66 mhz; i out = 0 ma; cs = v il , v cc = max 11 16 ma f = 66 mhz; i out = 0 ma; cs = v il , v cc = max 10 15 f = 50 mhz; i out = 0 ma; cs = v il , v cc = max 914 f = 33 mhz; i out = 0 ma; cs = v il , v cc = max 812 f = 20 mhz; i out = 0 ma; cs = v il , v cc = max 710 i cc2 active current, program operation cs = v cc , v cc = max 12 18 ma i cc3 active current, erase operation cs = v cc , v cc = max 14 20 ma i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v
32 3677f?dflash?5/2013 at25df021 v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6 ma; v cc = min 0.4 v v oh output high voltage i oh = -100 a; v cc = min v cc - 0.2v v 14.4 ac characteristics - maximum clock frequencies symbol parameter at25df021 (2.3v version) at25df021 (2.7v version) units min max min max f clk maximum clock frequency for all operations (excluding 03h opcode) 50 66 mhz f rdlf maximum clock frequency for 03h opcode (read array ? low frequency) 33 33 mhz 14.5 ac characteristics ? all other parameters symbol parameter at25df021 (2.3v version) at25df021 (2.7v version) units min max min max t clkh clock high time 8.0 6.4 ns t clkl clock low time 8.0 6.4 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 0.1 v/ns t csh chip select high time 50 50 ns t csls chip select low setup time (relative to clock) 5 5 ns t cslh chip select low hold time (relative to clock) 5 5 ns t cshs chip select high setup time (relative to clock) 5 5 ns t cshh chip select high hold time (relative to clock) 5 5 ns t ds data in setup time 2 2 ns t dh data in hold time 3 3 ns t dis (1) output disable time 7 6 ns t v (2) output valid time 7 6 ns t oh output hold time 0 0 ns t hls hold low setup time (relative to clock) 5 5 ns t hlh hold low hold time (relative to clock) 5 5 ns t hhs hold high setup time (relative to clock) 5 5 ns t hhh hold high hold time (relative to clock) 5 5 ns t hlqz (1) hold low to output high-z 7 6 ns t hhqx (1) hold high to output low-z 7 6 ns 14.3 dc characteristics (continued) symbol parameter condition min typ max units
33 3677f?dflash?5/2013 at25df021 notes: 1. not 100% tested (value guaranteed by design and characterization). 2. 15 pf load at frequencies above 66 mhz, 30 pf otherwise. 3. only applicable as a constraint for the write status register command when sprl = 1. note: 1. maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. not 100% tested (value guaranteed by design and characterization). t wps (1)(3) write protect setup time 20 20 ns t wph (1)(3) write protect hold time 100 100 ns t secp (1) sector protect time (from chip select high) 20 20 ns t secup (1) sector unprotect time (from chip select high) 20 20 ns t edpd (1) chip select high to deep power-down 3 3 s t rdpd (1) chip select high to standby mode 30 30 s 14.6 program and erase characteristics symbol parameter min typ max units t pp (1) page program time (256 bytes) 1.0 5.0 ms t bp byte program time 7 s t blke (1) block erase time 4 kbytes 50 200 ms 32 kbytes 250 600 64 kbytes 450 950 t chpe (1)(2) chip erase time 2.0 3.5 sec t otpp (1) otp security register program time 200 500 s t wrsr (2) write status register time 200 ns 14.7 power-up conditions symbol parameter min max units t vcsl minimum v cc to chip select low time 1.2 ms t puw power-up device delay before program or erase allowed 10 ms v por power-on reset voltage 1.5 2.2 v 14.5 ac characteristics ? all other parameters (continued) symbol parameter at25df021 (2.3v version) at25df021 (2.7v version) units min max min max
34 3677f?dflash?5/2013 at25df021 14.8 input test waveforms and measurement levels 14.9 output test load ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under test 15 pf (frequencies above 66 mhz) or 30pf
35 3677f?dflash?5/2013 at25df021 15. ac waveforms figure 15-1. serial input timing figure 15-2. serial output timing figure 15-3. wp timing for write status register command when sprl = 1 cs si sck so msb high-impedance msb lsb t csls t clkh t clkl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t clkh t clkl t dis t v t oh wp si sck so 000 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode
36 3677f?dflash?5/2013 at25df021 figure 15-4. hold timing ? serial input figure 15-5. hold timing ? serial output cs si sck so t hhh t hls t hlh t hhs hold high-impedance cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx
37 3677f?dflash?5/2013 at25df021 16. ordering information 16.1 ordering code detail note: the shipping carrier option code is not marked on the devices. at2 5d 0 2 ssh b 1 | f | f designator product family device density 02 = 2-megabit interface 1 = serial package option ss = 8-lead, 0.150" wide soic m = 8-pad 5 x 6 x 0.6 mm udfn device grade h = green, nipdau lead finish, industrial temperature range (?40c to +85c) shipping carrier option b = bulk (tubes) y = bulk (trays) t = tape and reel operating voltage blank = 2.7v minimum (2.7v to 3.6v) f = 2.3v minimum (2.3v to 3.6v) 16.2 green package options (pb/halide-free/rohs compliant) ordering code package lead finish operating voltage max. freq. (mhz) operation range at25df021-ssh-b at25df021-ssh-t 8s1 nipdau 2.7v to 3.6v 70 industrial (-40c to +85c) at25df021-mh-y AT25DF021-MH-T 8ma1 at25df021-sshf-b at25df021-sshf-t 8s1 nipdau 2.3v to 3.6v 50 at25df021-mhf-y at25df021-mhf-t 8ma1 package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8ma1 8-pad, 5 x 6 x 0.6 mm, thermally enhanced ultra thin dual flat no lead package (udfn)
38 3677f?dflash?5/2013 at25df021 17. packaging information 17.1 8s1 ? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: contact@adestotech.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
39 3677f?dflash?5/2013 at25df021 17.2 8ma1 ? udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8ma1 yfg d 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max n o t e a 0.45 0.55 0.60 a1 0.00 0.02 0.05 b 0.35 0.40 0.48 c 0.152 ref d 4.90 5.00 5.10 d2 3.80 4.00 4.20 e 5.90 6.00 6.10 e2 3.20 3.40 3.60 e 1.27 l 0.50 0.60 0.75 y 0.00 ? 0.08 k 0.20 ? ? 4/15/08 pin 1 id top view e d a1 a side view y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) 0.45 k pin #1 cham f e r (c 0.35) option a (option b)
40 3677f?dflash?5/2013 at25df021 18. revision history revision level ? release date history a ? february 2008 initial release b ? may 2008 changed deep power-down current specifications ? changed typical value from 4 a to 8 a ? changed maximum value from 8 a to 15 a changed typical 64 kb block erase time from 400 ms to 450 ms changed typical chip erase time from 1.5s to 2.0s changed t vcsl time from 1.0 ms minimum to 1.2 ms minimum changed v por maximum from 2.5v to 2.2v c ? september 2008 removed ?preliminary? designation from datasheet changed maximum clock frequency from 70 mhz to 66 mhz changed maximum standby current value from 35 a to 50 a changed deep power-down current specifications ? changed typical value from 8 a to 15 a ? changed maximum value from 15 a to 25 a d ? april 2009 added system considerations section e ? november 2012 update to adesto f ? may 2013 added ?not recommended for new designs?. updated logo, and copyright date.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2013 adesto technologies. all rights reserved. / rev.: 3677f?dflash?5/2013 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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